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Project: Fault-Tolerant LDPC Decoders

Error-correction codes (and particularly capacity-approaching codes like LDPC codes) are used to dramatically reduce the signal power on a communication link, but powerful codes also typically require a significant amount of energy to be decoded at the receiver. It is therefore highly desirable to reduce the energy consumption of such powerful ECC decoders, particularly in the context of IoT and sensor networks applications where both the transmitter and the receiver might be ultra-low power devices.

Our contributions have shown that we can accurately characterize the faults caused by occasional timing violations in the synchronous processing units of a decoder. This characterization can then be used to predict the performance of a faulty decoders for hypothetical infinite-length LDPC codes but also for finite-length codes. Finally, the use of faulty circuits reduces energy consumption for the same quality of output.

Some publications:

  • F. Leduc-Primeau, F. R. Kschischang and W. J. Gross. “Modeling and Energy Optimization of LDPC Decoder Circuits with Timing Violations,” IEEE Transactions on Communications, vol. 66, no. 3, pp. 932-946, Mar. 2018. (IEEEXplore) (arXiv)
  • F. Leduc-Primeau and W. J. Gross. “Finite-Length Quasi-Synchronous LDPC Decoders,” in 9th Int. Symp. on Turbo Codes and Iterative Information Processing, Sep. 2016. (IEEEXplore)

Together with my collaborator Elsa Dupraz, we are taking this research further in our Energy-First Forward Error-Correction project (EF-FECtive), funded by ANR in France. The first publication within this project presents a novel decoder architecture and an approach for reducing decoding latency:

  • E. Dupraz, F. Leduc-Primeau and F. Gagnon. “Low-Latency LDPC Decoding Achieved by Code and Architecture Co-Design,” in 10th Int. Symp. on Turbo Codes and Iterative Information Processing, Dec. 2018. (Link 1) (IEEEXplore)

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en/faultyldpc.txt · Last modified: 2019/04/09 20:25 by francoislp